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freescale semiconductor data sheet: product preview document number: mpc5553 rev. 0, 06/2006 contents ? freescale semiconductor, inc., 2006. all rights reserved. ? preliminary?subject to change without notice this document contains information on a new pr oduct. specifications and information herein are subject to change without notice. this document provides electrical specifications, pin assignments, and package diagrams for the mpc5553 microcontroller device. for functional characteristics, refer to the mpc5553/mpc5554 microcontroller reference manual . 1 overview the mpc5553 microcontroller (mcu) is a member of the mpc5500 family of micr ocontrollers based on the powerpc? book e architecture. this family of parts contains many new featur es coupled with high performance cmos technology to provide substantial reduction of cost per feature and significant performance improvement over the mpc500 family. the host processor core of this device is compatible with the powerpc book e architecture . it is 100% user mode compatible (with floating point library) with the classic powerpc instruction set. the book e architecture has enhancements that improve the powerpc architecture?s fit in embedded applications. this core also has additional instructions, including digital signal processing (dsp) instruct ions, beyond the classic 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . 5 3.3 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 emi (electromagnetic interference) characteristics 9 3.5 esd characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 vrc/por electrical specifications . . . . . . . . . . . . 10 3.7 power up/down sequencing. . . . . . . . . . . . . . . . . 11 3.8 dc electrical specifications. . . . . . . . . . . . . . . . . . 13 3.9 oscillator & fmpll electric al characteristics . . . . 19 3.10 eqadc electrical characteristics . . . . . . . . . . . . . 20 3.11 h7fa flash memory electr ical characteristics . . . 21 3.12 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13 ac timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 fast ethernet ac timing specifications . . . . . . . . 45 4 mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.1 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.2 package dimensions. . . . . . . . . . . . . . . . . . . . . . . 55 5 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 mpc5553 microcontroller data sheet by: microcontroller division
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice overview freescale semiconductor 2 powerpc instruction set. this fami ly of parts contains many new feat ures coupled with high performance cmos technology to provide significant performance improveme nt over the mpc565. the mpc5553 of the mpc5500 family has two levels of memory hierarchy. the fa stest accesses are to the 8-kilobyte unified cache. the next level in the hierarchy contains the 64-kilobyte on-chip internal sram and 1.5 mbyte internal flash memory. both the internal sram and the flash memory can hold instructions and data. the external bus interface ha s been designed to support most of the standard memories used with the mpc5xx family. the complex i/o timer functions of the mpc5500 famil y are performed by an enhanced time processor unit engine (etpu). the et pu engine controls 32 ha rdware channels. the etpu has been enhanced over the tpu by providing 24-bit timers, doubl e action hardware cha nnels, variable number of parameters per channel, angle clock hardware, a nd additional control and arithmetic instructions. the etpu can be programmed using a high-le vel programming language. the less complex timer functions of the mpc5500 family are perf ormed by the enhanced modular input/output system (emios). the emios? 24 hard ware channels are capable of single action, double action, pulse width modulation (pwm), and modulus counter operation. motor control capabilities include edge-aligned and center-aligned pwm. off-chip communication is performed by a suite of se rial protocols including controller area networks (flexcans), enhanced deserial/seria l peripheral interfaces (dspi), a nd enhanced serial communications interfaces (escis). the dspis suppor t pin reduction through hardware seri alization and deserialization of timer channels and general-purpos e input/output (gpio) signals. the mcu of the mpc5553 has an on-chip 40-channel enhanced queued dual anal og-to-digital converter (eqadc). the system integration unit (siu) performs several chip-wide configuration f unctions. pad configuration and general-purpose input and output (g pio) are controlled from the si u. external interrupts and reset control are also found in the siu. the internal mu ltiplexer submodule (siu_dis r) provides multiplexing of eqadc trigger sources, daisy chaining the d spis and external interrupt signal multiplexing.
ordering information mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 3 2 ordering information figure 1. mpc5500 family part number example table 1. orderable part numbers freescale part number description speed (mhz) max speed 1 (mhz) (f max ) temperature mpc5553mvr132 mpc5553 lead free 416 package 132 132 -40 c to 125 c mpc5553mzp132 mpc5553 lead 416 package 132 132 -40 c to 125 c mpc5553mvz132 mpc5553 lead free 324 package 132 132 -40 c to 125 c mpc5553mzq132 mpc5553 lead 324 package 132 132 -40 c to 125 c mpc5553mvf132 mpc5553 lead 208 package 132 132 -40 c to 125 c mpc5553mvm132 mpc5553 lead free 208 package 132 132 -40 c to 125 c mpc5553mvr112 mpc5553 lead free 416 package 112 114 -40 c to 125 c mpc5553mzp112 mpc5553 lead 416 package 112 114 -40 c to 125 c mpc5553mvz112 mpc5553 lead free 324 package 112 114 -40 c to 125 c mpc5553mzq112 mpc5553 lead 324 package 112 114 -40 c to 125 c mpc5553mvf112 mpc5553 lead 208 package 112 114 -40 c to 125 c mpc5553mvm112 mpc5553 lead free 208 package 112 114 -40 c to 125 c mpc5553mvr80 mpc5553 lead free 416 package 80 82 -40 c to 125 c mpc5553mzp80 mpc5553 lead 416 package 80 82 -40 c to 125 c mpc5553mvz80 mpc5553 lead free 324 package 80 82 -40 c to 125 c mpc5553mzq80 mpc5553 lead 324 package 80 82 -40 c to 125 c mpc m 80r2 qualification status core code device number temperature range package identifier operating frequency (mhz) tape and reel status temperature range m = -40 c to 125 c a = -55 c to 125 c package identifier zp = 416pbga snpb vr = 416pbga pb-free vf = 208mapbga snpb vm = 208mapbga pb-free zq = 324pbga snpb vz = 324pbga pb-free operating frequency 80 = 80mhz 112 = 112mhz 132 = 132mhz note: not all options are available on all devices. refer to ta b l e 1 . tape and reel status r2 = tape and reel (blank) = trays qualification status p = pre qualification m = full spec qualified 5553 zp
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 4 3 electrical characteristics this section contains detailed information on power c onsiderations, dc/ac electric al characteristics, and ac timing specifications for the mcu. 3.1 maximum ratings mpc5553mvf80 mpc5553 lead 208 package 80 82 -40 c to 125 c mpc5553mvm80 mpc5553 lead free 208 package 80 82 -40 c to 125 c 1 speed is the nominal maximum frequency. max speed is the maximum speed allowed including any frequency modulation. 80-mhz parts allow for 80 mhz + 2% modulation. however, 132-mhz allows only 128 mhz + 2% fm. table 2. absolute maximum ratings 1 num characteristic symbol min max 2 unit 1 1.5v core supply voltage 3 v dd ? 0.3 1.7 v 2 flash program/erase voltage v pp ? 0.3 6.5 v 3 flash core voltage v ddf ? 0.3 1.7 v 4 flash read voltage v flash ? 0.3 4.6 v 5 sram standby voltage v stby ? 0.3 1.7 v 6 clock synthesizer voltage v ddsyn ? 0.3 4.6 v 7 3.3v i/o buffer voltage v dd33 ?0.3 4.6 v 8 voltage regulator control input voltage v rc33 ?0.3 4.6 v 9 analog supply voltage (reference to v ssa )v dda ? 0.3 5.5 v 10 i/o supply voltage (fast i/o pads) 4 v dde ? 0.3 4.6 v 11 i/o supply voltage (slow/medium i/o pads) 4 v ddeh ? 0.3 6.5 v 12 dc input voltage 5 vddeh powered i/o pads, except etpub15 and sinb (dspi_b_sin) vddeh powered i/o pads (etpub15 and sinb) vdde powered i/o pads v in ?1.0 6 ?0.3 7 ?1.0 6 6.5 8 6.5 8 4.6 9 v 13 analog reference high voltage (reference to vrl) v rh ? 0.3 5.5 v 14 vss differential voltage v ss ? v ssa ? 0.1 0.1 v 15 vdd differential voltage v dd ? v dda ? v dda v dd v 16 v ref differential voltage v rh ? v rl ? 0.3 5.5 v 17 v rh to vdda differential voltage v rh ? v dda ? 5.5 5.5 v 18 v rl to vssa differential voltage v rl ? v ssa ? 0.3 0.3 v 19 v ddeh to v dda differential voltage v ddeh ? v dda ?v dda v ddeh v 20 v ddf to v dd differential voltage v ddf ? v dd ?0.3 0.3 v 21 this spec has been moved to ta b l e 9 , spec 43a. 22 vsssyn to vss differential voltage v sssyn ? v ss ?0.1 0.1 v table 1. orderable part numbers (continued)
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 5 3.2 thermal characteristics 23 v rcvss to v ss differential voltage v rcvss ? v ss ?0.1 0.1 v 24 maximum dc digital input current 10 (per pin, applies to all digital pins) 5 i maxd ?2 2 ma 25 maximum dc analog input current 11 (per pin, applies to all analog pins) i maxa ?3 3 ma 26 maximum operating temperature range 12 ? die junction temperature t j ? 40.0 150.0 o c 27 storage temperature range t stg ? 55.0 150.0 o c 28 maximum solder temperature 13 t sdr ? 260.0 o c 29 moisture sensitivity level 14 msl ? 3 1 functional operating conditions are given in the dc electrical s pecifications. absolute maximum ratings are stress ratings only , and functional operation at the maxima is not guaranteed. stre ss beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 absolute maximum voltages are currently maximum burn-in voltage s. absolute maximum specificat ions for device stress have not yet been determined. 3 1.5v +/? 10% for proper operation. this parameter is specified at a maximum junction temperature of 150c. 4 all functional non-supply i/o pins are clamped to vss and vdde or vddeh. 5 ac signal over and undershoot of the input voltages of up to +/ ? 2.0 volts is permitted for a cumulative duration of 60 hours over the complete lifetime of the device (injection current does not need to be limited for this duration). 6 internal structures will hold the voltage above ?1.0 vo lt if the injection current limit of 1 ma is met. 7 internal structures will not clamp to a safe voltage. external protection must be used to ensure that voltage on the pin stays above ?0.3 volts. 8 internal structures hold the input voltage below this maximum voltage on all pads powered by vddeh supplies, if the maximum injection current specification is met (1 ma for all pi ns) and vddeh is within operat ing voltage specifications. 9 internal structures hold the input voltage below this maximum voltage on all pads powered by vdde supplies, if the maximum injection current specification is met (1 ma for all pi ns) and vdde is within operat ing voltage specifications. 10 total injection current for all pins (including both digital and analog) must not exceed 25ma. 11 total injection current for all anal og input pins must not exceed 15ma. 12 lifetime operation at these specif ication limits is not guaranteed. 13 solder profile per cdf-aec-q100. 14 moisture sensitivity per jedec test method a112. table 3. thermal characteristics num characteristic symbol unit value 208 mapbga 324 pbga 416 pbga 1 junction to ambient 1, 2 natural convection (single layer board) r ja c/w 41 30 29 2 junction to ambient 1, 3 natural convection (four layer board 2s2p) r ja c/w 25 21 21 table 2. absolute maximum ratings 1 (continued) num characteristic symbol min max 2 unit
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 6 3.2.1 general notes for specifications at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) where: t a = ambient temperature for the package ( o c) r ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the supplied thermal resistances ar e provided based on jedec jesd51 series of standards to provide consistent values for estimations and comparisons. th e difference between the va lues determined on the single-layer (1s) board and on the four-layer board wi th two signal layers and a power and a ground plane (2s2p) clearly demonstrate that the effective thermal resistance of the component is not a constant. it depends on the construction of the a pplication board (number of planes), the effective size of the board which cools the component, how well the component is thermally and elec trically connected to the planes, and the power being dissipat ed by adjacent components. connect all the ground and powe r balls to the resp ective planes with one via pe r ball. using fewer vias to connect the package to the planes reduces the thermal performance. thinner planes also reduce the thermal 3 junction to ambient 1, 3 (@200 ft./min., single layer board) r jma c/w 33 24 23 4 junction to ambient 1, 3 (@200 ft./min., four layer board 2s2p) r jma c/w 22 17 18 5 junction to board 4 (four layer board 2s2p) r jb c/w 15 12 13 6 junction to case 5 r jc c/w 7 8 9 7 junction to package top 6 natural convection jt c/w 2 2 2 1 junction temperature is a function of on-chip power di ssipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissi pation of other components on the board, and board thermal resistance. 2 per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circ uit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1) with the cold plate temperature used for the case temperature. 6 thermal characterization parameter indicating the temp erature difference between package top and the junction temperature per jedec jesd51-2. table 3. thermal characteristics (continued) num characteristic symbol unit value 208 mapbga 324 pbga 416 pbga
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 7 performance. when the clearance between through vi as leave the planes virtually disconnected, the thermal performance is also greatly reduced. as a general rule, the value obtaine d on a single layer board is appropria te for the tightly packed printed circuit board. the value obtained on the board with th e internal planes is usually appropriate if the application board has one oz (35 micron nominal thickness) internal planes, the components are well separated, and the overall power dissipa tion on the board is less than 0.02 w/cm 2 . the thermal performance of any component depe nds strongly on the power dissipation of surrounding components. in addition, th e ambient temperature varies widely wi thin the application. for many natural convection and especially closed box applications, the board temperatur e at the perimeter (edge) of the package is approximately the same as the local ai r temperature near the device. specifying the local ambient conditions explicitly as the board temperatur e provides a more precise description of the local ambient conditions that determine the temperature of the device. at a known board temperature, th e junction temperature is estima ted using the following equation: t j = t b + (r jb p d ) where: t j = junction temperature ( o c) t b = board temperature at the package perimeter ( o c/w) r jb = junction to board thermal resistance ( o c/w) per jesd51-8 p d = power dissipation in the package (w) when the heat loss from the package case to the ai r can be ignored, acceptable predictions of junction temperature can be made. the appli cation board should be similar to the thermal test condition, with the component soldered to a bo ard with internal planes. historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ja = r jc + r ca where: r ja = junction to ambient thermal resistance ( o c/w) r jc = junction to case thermal resistance ( o c/w) r ca = case to ambient thermal resistance ( o c/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambien t thermal resistance, r ca . for instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printe d circuit board, or change the thermal dissipation on the printed circ uit board surrounding the de vice. this description is most useful for packages with heat sinks wh ere some 90% of the heat flow is through the case to the heat sink to ambient. for most packages, a better model is required. a more accurate two-resistor th ermal model can be constructed fr om the junction to board thermal resistance and the junction to case thermal resistance . the junction to case cove rs the situation where a heat sink will be used or where a s ubstantial amount of heat is dissipated from the top of the package. the junction to board thermal re sistance describes the thermal performan ce when most of th e heat is conducted
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 8 to the printed circuit board. this mode l can be used for either hand esti mations or for a computational fluid dynamics (cfd) thermal model. to determine the junction temperatur e of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine th e junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt p d ) where: t t = thermocouple temperature on top of the package ( o c) jt = thermal characterization parameter ( o c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specificati on using a 40-gauge type t thermocouple epoxied to the top center of the pack age case. the thermocouple should be positioned so that the thermocouple junction rests on the packag e. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from th e junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. references: semiconductor equipment and materials inte rnational 805 east middlefield rd mountain view, ca 94043 (415) 964-5111 mil-spec and eia/jesd (jedec) spec ifications are available from global engineering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org . ? 1. c.e. triplett and b. joiner, ?an experime ntal characterization of a 272 pbga within an automotive engine controller module,? pr oceedings of semitherm, san diego, 1998, pp. 47?54. ? 2. g. kromann, s. shidore, and s. addison, ?thermal modeling of a pbga for air-cooled applications,? electr onic packaging and production, pp. 53?58, march 1998. ? 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedi ngs of semitherm, san diego, 1999, pp. 212?220. 3.3 package the mpc5553 is available in packaged form. package options are listed in section 2, ?ordering information .? refer to section 4, ?mechanicals,? for pinouts and package drawings.
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 9 3.4 emi (electromagnetic interference) characteristics 3.5 esd characteristics table 4. emi testing specifications 1 1 emi testing and i/o port waveforms per sae j1752/3 issued 1995- 03. qualification testing is performed on the mpc5554 and applied to mpc5500 family as generic emi performance data. num characteristic min. value typ. value max. value unit 1 scan range 0.15 ? 1000 mhz 2 operating frequency ? ? 132 mhz 3v dd operating voltages ? 1.5 ? v 4v ddsyn , v rc33 , v dd33 , v flash , v dde operating voltages ? 3.3 ? v 5 vpp, vddeh, vdda operating voltages ? 5.0 ? v 6 maximum amplitude ? ? 14 2 32 3 2 as measured with ?single-chip? emi program. 3 as measured with ?expanded? emi program. dbuv 7 operating temperature ? ? 25 o c table 5. esd ratings 1, 2 1 all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer m eets the device specification requirements. complete dc parametric and f unctional testing shall be performed per a pplicable device specification at room temperature followed by hot temperature, unless s pecified otherwise in the device specification characteristic symbol value unit esd for human body model (hbm) 2000 v hbm circuit description r1 1500 ohm c100 pf esd for field induced charge model (fdcm) 500 (all pins) v 750 (corner pins) number of pulses per pin: positive pulses (hbm) negative pulses (hbm) ? ? 1 1 ? ? interval of pulses ? 1 second
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 10 3.6 vrc/por electrical specifications table 6. vrc/por electr ical specifications num characteristic symbol min max units 1 1.5v (vdd) por negated (ramp up) 1.5v (vdd) por asserted (ramp down) v_por15 1.1 1.1 1.35 1.35 v 2 3.3v (vddsyn) por negated (ramp up) 3.3v (vddsyn) por asserted (ramp down) v_por33 2.0 2.0 2.85 2.85 v 3 reset pin supply (vddeh6) por negated (ramp up) reset pin supply (vddeh6) por asserted (ramp down) v_por5 2.0 2.0 2.85 2.85 v 4 vrc33 voltage before regulator controller allows the pass transistor to start turning on v_trans_ start 1.0 2.0 v 5 vrc33 voltage when regulator controller allows the pass transistor to completely turn on 1, 2 1 user must be able to supply full operating current fo r the 1.5v supply when the 3.3v supply reaches this range. 2 current limit may be reached during ramp up and should not be treated as short circuit current. v_trans_on 2.0 2.85 v 6 vrc33 voltage above which the regulator controller will keep the 1.5v supply in regulation 3, 4 3 at peak current for device. 4 assumes that the freescale recommended board requirement s and transistor recommendations are met. board signal traces/routing from the vrcctl pa ckage signal to the base of the external pass transistor and between the emitter of the pass transistor to the vdd package signals should have a maximu m of 100 nh inductance and minimal resistance (<1 ohm). vrcctl should have a nominal 1 f phase compensation capacitor to ground. vdd should have a 20 f (nominal) bulk capacitor (> 4 f over all conditions, including lifetime). high frequency bypass capacitors consisting of eight 0.01 f, two 0.1 f, and one 1 f capacitors should be place around the package on the vdd supply signals. v_vrc33reg 3.0 ? v 7 current which can be sourced by vrcctl i_vrcctl 5 5 i_vrcctl measured at the following condit ions: vdd=1.35v, vrc33= 3.1v, v_vrcctl=2.2v. ma ? 40c 11.0 ? ma 25c 9.0 ? ma 150c (tj) 7.5 ? ma 8 voltage differential during power up that vdd33 can lag vddsyn or vddeh6 before vddsyn and vddeh6 reach v_por33 and v_por5 minimums respectively vdd33_lag ? 1.0 v 9 absolute value of slew rate on power supply pins ? 50 v/ms 10 required gain: idd / i_vrcctl (@vdd = 1.35v, f sys = 132mhz) 4, 6 6 values are based on idd from high use applications as explained in the idd electrical specification. beta 7 7 beta is measured on a per part basis and is calculated as i dd / i_vrcctl and represents the worst case external transistor beta. ? 40c 55.0 8 8 preliminary value. final specification pending characterization. ?? 25c 58.0 8 ?? 150c (tj) 70.0 8 500 ?
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 11 3.7 power up/down sequencing power sequencing between the 1.5-v power supply and vddsyn or the reset power supplies is required if the user provides an external 1.5-v power supply and ties vrc33 to ground. to avoid this power sequencing requirement, power up vrc33 within the specified operating range, even if not using the on-chip voltage regulat or controller. refer to section 3.7.1, ?power up sequence (if vrc33 grounded)? and section 3.7.2, ?power down sequence (if vrc33 grounded) . ? another power sequencing requirement is that vdd33 must be of suffic ient voltage before por negates, so that the values on certain pins are treat ed as 1s when por does negate. refer to section 3.7.3, ?input value of pins during por dependent on vdd33 . ? although there is no power sequenci ng required between vrc33 and vd dsyn during power up, for the vrc stage turn-on to operate with in specification, vrc33 must not lead vddsyn by more than 600 mv or lag by more than 100 mv. higher spikes in the emitter current of the pass transi stor will occur if vrc33 leads or lags vddsyn by more than these amounts. th e value of that higher spike in current depends on the board power supply circuitry and th e amount of board level capacitance. furthermore, when all of the pors negate, the syst em clock will start to toggle, adding another large increase of the current consumption from vrc33. if vrc33 lags vddsyn by more than 100 mv, this increased current consumption can drop vdd low enough to assert the 1.5-v por again. oscillations are even possible because when the 1.5-v por asserts, the system clock stops, causing the voltage on vdd to rise until the 1.5-v por negates again. any oscillations stop when vrc33 is powered sufficiently. when powering down, vrc33 and vddsyn do not have a delta requirement to each other, because the bypass capacitors internal and external to the device are already charged. when not powering up or down, vrc 33 and vddsyn do not have a delta requirement to each other for the vrc to operate within specification. although there are no power up/down seque ncing requirements to prevent is sues like latch-up, excessive current spikes, etc., the state of the i/o pins during power up/down vari es depending on power. table 7 gives the pin state for the sequence cases for all pins with pad type pa d_fc (fast type), and table 8 for all pins with pad type pad_mh (medium type) and pad_sh (slow type). table 7. power sequence pin states (fast pads) v dde v dd33 v dd pad_fc (fast) output driver state comment low x x low functional i/o pins are clamped to vss and vdde vdde low x high vdde vdd33 low high impedance por asserted. vdde vdd33 vdd functional no por asserted
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 12 3.7.1 power up sequence (if vrc33 grounded) in this case, the 1.5-v vdd supply must rise to 1.35-v before the 3.3-v vdds yn and the reset power supplies rises above 2.0 v. this ensure s that digital logic in the pll on the 1.5-v supply wi ll not begin to operate below the specified operation range lower limit of 1.35 v. since th e internal 1.5-v por is disabled, the internal 3.3-v por or the res et power por must be depended on to hold the device in reset. since they may negate as low as 2.0 v, it is necessary fo r vdd to be within spec before the 3.3-v por and the reset por negate. figure 2. power up sequence if vrc33 grounded 3.7.2 power down sequen ce (if vrc33 grounded) in this case, the only requirement is that if vdd falls below its ope rating range, vddsyn or the reset power must fall below 2.0 v before vdd is allowed to rise ba ck into its operating ra nge. this ensures that digital 1.5-v logic that is only reset by ored_por, wh ich may have been affected by the 1.5v supply falling below spec, is reset properly. 3.7.3 input value of pins du ring por dependent on vdd33 in order to avoid accidenta lly selecting the bypass clock because pllcfg[0:1] and rstcfg are not treated as 1s when por negates, vdd33 must not lag vddsyn and the reset pin power (vddeh6) when powering the device by more th an the vdd33 lag specification in table 6 . vdd33 individually can lag either vddsyn or the rese t pin power (vddeh6) by more th an the vdd33 lag specification. vdd33 can lag one of the vddsyn or vddeh6 supplie s, but cannot lag both by more than the vdd33 lag specification. this vdd33 lag specification onl y applies during power up. vdd33 has no lead or lag requirements when powering down. table 8. power sequence pin states (medium and slow pads) v ddeh v dd pad_mh/pad_sh (medium and slow) output driver comment low x low functional i/o pins are clamped to vss and vddeh vddeh low high impedance por asserted vddeh vdd functional no por asserted vddsyn and reset power vdd 2.0v 1.35v vdd must reach 1.35v before vddsyn and the reset power reach 2.0v
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 13 3.8 dc electrical specifications table 9. dc electrical specifications num characteristic symbol min max unit 1 core supply voltage (average dc rms voltage) v dd 1.35 1.65 v 2 i/o supply voltage (fast i/o) v dde 1.62 3.6 v 3 i/o supply voltage (slow/medium i/o) v ddeh 3.0 5.25 v 4 3.3v i/o buffer voltage v dd33 3.0 3.6 v 5 voltage regulator c ontrol input voltage v rc33 3.0 3.6 v 6 analog supply voltage 1 v dda 4.5 5.25 v 8 flash programming voltage 2 vpp 4.5 5.25 v 9 flash read voltage vflash 3.0 3.6 v 10 sram standby voltage 3 vstby 0.8 1.2 v 11 clock synthesizer operating voltage vddsyn 3.0 3.6 v 12 fast i/o input high voltage v ih_f 0.65 * v dde v dde + 0.3 v 13 fast i/o input low voltage v il_f v ss ? 0.3 0.35 * v dde v 14 medium/slow i/o input high voltage v ih_s 0.65 * v ddeh v ddeh + 0.3 v 15 medium/slow i/o input low voltage v il_s v ss ? 0.3 0.35 * v ddeh v 16 fast i/o input hysteresis v hys_f 0.1 * v dde v 17 medium/slow i/o input hysteresis v hys_s 0.1 * v ddeh v 18 analog input voltage v indc vssa ? 0.3 vdda + 0.3 v 19 fast i/o output high voltage (i oh_f = ?2.0ma) v oh_f 0.8 * vdde ? v 20 slow/medium i/o output high voltage (i oh_s = ?2.0ma) v oh_s 0.8 * vddeh ?v 21 fast i/o output low voltage (i ol_f = 2.0ma) v ol_f ? 0.2 * vdde v 22 slow/medium i/o output low voltage (i ol_s = 2.0ma) v ol_s ? 0.2 * vddeh v 23 load capacitance (fast i/o) 4 dsc(siu_pcr[8:9]) = 0b00 dsc(siu_pcr[8:9]) = 0b01 dsc(siu_pcr[8:9]) = 0b10 dsc(siu_pcr[8:9]) = 0b11 c l ? ? ? 10 20 30 50 pf pf pf pf 24 input capacitance (digital pins) c in ?7pf 25 input capacitance (analog pins) c in_a ?10pf
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 14 26 input capacitance (shared digital and analog pins an12_ma0_sds, an12_ma1_sdo, an14_ma2_sdi, and an15_fck) c in_m ?12pf 27a operating current 5 1.5v supplies @ 132mhz: vdd (including vddf max current) 6, 7 @1.65v typical use vdd (including vddf max current) 6 , 7 @1.35v typical use vdd (including vddf max current) 7 , 8 @1.65v high use vdd (including vddf max current) 7 , 8 @1.35v high use idd idd idd idd ? ? ? ? 550 9 450 9 600 9 490 9 ma ma ma ma 27b operating current 5 1.5v supplies @ 114mhz: vdd (including vddf max current) 6 , 7 @1.65v typical use vdd (including vddf max current) 6 , 7 @1.35v typical use vdd (including vddf max current) 7 , 8 @1.65v high use vdd (including vddf max current) 7 , 8 @1.35v high use idd idd idd idd ? ? ? ? 460 9 380 9 520 9 420 9 ma ma ma ma 27c operating current 5 1.5v supplies @ 82mhz: vdd (including vddf max current) 6 , 7 @1.65v typical use vdd (including vddf max current) 6 , 7 @1.35v typical use vdd (including vddf max current) 7 , 8 @1.65v high use vdd (including vddf max current) 7 , 8 @1.35v high use idd idd idd idd ? ? ? ? 350 9 290 9 400 9 330 9 ma ma ma ma 27d idd stby @ 25c vstby @ 0.8v vstby @ 1.0v vstby @ 1.2v idd stby @ 60c vstby @ 0.8v vstby @ 1.0v vstby @ 1.2v idd stby @ 150c (tj) vstby @ 0.8v vstby @ 1.0v vstby @ 1.2v idd stby idd stby idd stby idd stby idd stby idd stby idd stby idd stby idd stby ? ? ? ? ? ? ? ? ? 20 30 50 70 100 200 1200 1500 2000 a a a a a a a a a 28 operating current 3.3v supplies @ 132mhz: vdd33 10 idd 33 ? 2 + values derived from procedure of footnote 10 ma vflash i vflash ?10ma vddsyn i ddsyn ?15ma table 9. dc electrical specifications (continued) num characteristic symbol min max unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 15 29 operating current 5.0v suppl ies @ 132mhz (12mhz adclk): vdda (vdda0 + vdda1) analog reference supply current (vrh, vrl) vpp idd a i ref i pp ? ? ? ? 20.0 1.0 25 ma ma ma 30 operating current vdde 11 supplies: vddeh1 vdde2 vdde3 vddeh4 vdde5 vddeh6 vdde7 vddeh8 vddeh9 idd1 idd2 idd3 idd4 idd5 idd6 idd7 idd8 idd9 ? ? ? ? ? ? ? ? ? see footnote 11 ma ma ma ma ma ma ma ma ma 31 fast i/o weak pull up current 12 1.62v ? 1.98v 2.25v ? 2.75v 3.0v ? 3.6v i act_f 10 20 20 110 130 170 a a a fast i/o weak pull down current 12 1.62v ? 1.98v 2.25v ? 2.75v 3.0v ? 3.6v 10 20 20 100 130 170 a a a 32 slow/medium i/o weak pull up/down current 13 3.0v ? 3.6v 4.5v ? 5.5v i act_s 10 20 150 170 a a 33 i/o input leakage current 14 i inact_d ? 2.5 2.5 a 34 dc injection current (per pin) i ic ? 2.0 2.0 ma 35 analog input current, channel off 15 i inact_a ?150 150 na 35a analog input current, shared analog/digital pins (an12, an13, an14, an15) i inact_ad ? 2.5 2.5 a 36 vss differential voltage 16 vss ? vssa ? 100 100 mv 37 analog reference low voltage vrl vssa ? 0.1 vssa + 0.1 v 38 vrl differential voltage vrl ? vssa ?100 100 mv 39 analog reference high voltage vrh vdda ? 0.1 vdda + 0.1 v 40 v ref differential voltage vrh ? vrl 4.5 5.25 v 41 vsssyn to vss differential voltage vsssyn ? vss ?50 50 mv 42 vrcvss to vss differential voltage vrcvss ? vss ?50 50 mv 43 vddf to vdd differential voltage 2 vddf ? vdd ?100 100 mv table 9. dc electrical specifications (continued) num characteristic symbol min max unit
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 16 3.8.1 i/o pad current specifications the power consumption of an i/o se gment depends on the usage of the pi ns on a particular segment. the power consumption is the sum of al l output pin currents for a particul ar segment. the output pin current can be calculated from table 10 based on the voltage, frequency, and lo ad on the pin. use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 10 . 43a vrc33 to vddsyn differential voltage v rc33 ? v ddsyn ?0.1 0.1 17 v 44 analog input differential signal range (with common mode 2.5v) v idiff ? 2.5 2.5 v 45 operating temperature range ? ambient (packaged) t a (t l to t h ) ? 40.0 125.0 c 46 slew rate on power supply pins ? ? 50 v/ms 1 | vdda0?vdda1 | must be < 0.1v 2 vpp can drop to 3.0 volts during read operations. 3 during standby operation. if standby operation is not required, vstby can be connected to ground. 4 applies to clkout, external bus pins, and nexus pins. 5 maximum average rms dc current. 6 average current measured on automotive benchmark. 7 peak currents may be higher on specialized code. 8 high use current measured while running optimized spe assembly code with all code and data 100% locked in cache (0% miss rate) with all channels of the emios and etpu running aut onomously, plus the edma trans ferring data continuously from sram to sram. higher currents could be s een if an ?idle? loop that crosses cache lines is run from cache. code should be written to avoid this condition. 9 preliminary. final specification pending characterization. 10 power requirements for the vdd33 supply are dependent on t he frequency of operation and load of all i/o pins, and the voltages on the i/o segments. see ta b l e 1 1 for values to calculate power di ssipation for specific operation. 11 power requirements for each i/o segment are dependent on the frequ ency of operation and load of the i/o pins on a particular i/o segment, and the voltage of the i/o segment. see ta b l e 1 0 for values to calculate power dissipation for specific operation. the total power consumption of an i/o s egment is the sum of the individual power consumptions for each pin on the segment. 12 absolute value of current, measured at v il and v ih . 13 absolute value of current, measured at v il and v ih . 14 weak pull up/down inactive. measured at vdde = 3.6 v and vd deh = 5.25 v. applies to pad types: pad_fc, pad_sh, and pad_mh. 15 maximum leakage occurs at maximum operating temperature. le akage current decreases by approximately one-half for each 8 to 12 o c, in the ambient temperature range of 50 to 125 o c. applies to pad types: pad_a and pad_ae. 16 vssa refers to both vssa0 and vssa1 . | vssa0?vssa1 | must be < 0.1v 17 up to 0.6 volts during power up and power down. table 9. dc electrical specifications (continued) num characteristic symbol min max unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 17 3.8.2 i/o pad vdd33 current specifications the power consumption of the vdd33 supply dependent s on the usage of the pins on all i/o segments. the power consumption is the sum of all input and output pin vdd33 currents for all i/o segments. the output pin vdd33 current can be calculated from table 11 based on the voltage, frequency, and load on all fast (pad_fc) pins. th e input pin vdd33 current can be calculated from table 11 based on the voltage, table 10. i/o pad average dc current 1 1 these values are estimated from simulation and ar e not tested. currents apply to output pins only. num pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. voltag e (v) drive select / slew rate control current (ma) 1slowi drv_sh 25 50 5.25 11 8.0 210505.25013.2 3 2 50 5.25 00 0.7 4 2 200 5.25 00 2.4 5mediumi drv_mh 50 50 5.25 11 17.3 620505.25016.5 7 3.33 50 5.25 00 1.1 8 3.33 200 5.25 00 3.9 9fasti drv_fc 66 10 3.6 00 2.8 10 66 20 3.6 01 5.2 11 66 30 3.6 10 8.5 12 66 50 3.6 11 11.0 13 66 10 1.98 00 1.6 14 66 20 1.98 01 2.9 15 66 30 1.98 10 4.2 16 66 50 1.98 11 6.7 17 56 10 3.6 00 2.4 18 56 20 3.6 01 4.4 19 56 30 3.6 10 7.2 20 56 50 3.6 11 9.3 21 56 10 1.98 00 1.3 22 56 20 1.98 01 2.5 23 56 30 1.98 10 3.5 24 56 50 1.98 11 5.7 25 40 10 3.6 00 1.7 26 40 20 3.6 01 3.1 27 40 30 3.6 10 5.1 28 40 50 3.6 11 6.6 29 40 10 1.98 00 1.0 30 40 20 1.98 01 1.8 31 40 30 1.98 10 2.5 32 40 50 1.98 11 4.0
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 18 frequency, and load on all pad_sh and pad_sh pins. use li near scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in table 11 . table 11. vdd33 pad average dc current 1 1 these values are estimated from simulation and not tested. currents apply to output pins only for the fast pads and to input pins only for the slow and medium pads. num pad type symbol frequency (mhz) load 2 (pf) 2 all loads are lumped. v dd33 (v) v dde (v) drive select current (ma) inputs 1slowi 33_sh 66 0.5 3.6 5.5 na 0.003 2 medium i 33_mh 66 0.5 3.6 5.5 na 0.003 outputs 3fasti 33_fc 66 10 3.6 3.6 00 0.35 466203.63.6010.53 566303.63.6100.62 666503.63.6110.79 7 66 10 3.6 1.98 00 0.35 8 66 20 3.6 1.98 01 0.44 9 66 30 3.6 1.98 10 0.53 10 66 50 3.6 1.98 11 0.7 11 56 10 3.6 3.6 00 0.30 12 56 20 3.6 3.6 01 0.45 13 56 30 3.6 3.6 10 0.52 14 56 50 3.6 3.6 11 0.67 15 56 10 3.6 1.98 00 0.30 16 56 20 3.6 1.98 01 0.37 17 56 30 3.6 1.98 10 0.45 18 56 50 3.6 1.98 11 0.60 19 40 10 3.6 3.6 00 0.21 20 40 20 3.6 3.6 01 0.31 21 40 30 3.6 3.6 10 0.37 22 40 50 3.6 3.6 11 0.48 23 40 10 3.6 1.98 00 0.21 24 40 20 3.6 1.98 01 0.27 25 40 30 3.6 1.98 10 0.32 26 40 50 3.6 1.98 11 0.42
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 19 3.9 oscillator & fmpll electrical characteristics table 12. hip7 fmpll electrical specifications (v ddsyn = 3.0v to 3.6 v, v ss = v sssyn = 0 v, t a = t l to t h ) num characteristic symbol min. value max. value unit 1 pll reference frequency range: crystal reference external reference dual controller (1:1 mode) f ref_crystal f ref_ext f ref_1:1 8 8 24 20 20 f sys /2 mhz 2 system frequency 1 f sys f ico(min) 2 rfd f max 2 mhz 3 system clock period t cyc ?1 / f sys ns 4 loss of reference frequency 3 f lor 100 1000 khz 5 self clocked mode (scm) frequency 4 f scm 7.4 17.5 mhz 6 extal input high voltage crystal mode 5 all other modes (dual controller (1:1), bypass, external reference) v ihext v ihext vxtal + 0.4v ((vdde5/2) + 0.4v) ? ? v v 7 extal input low voltage crystal mode 6 all other modes (dual controller (1:1), bypass, external reference) v ilext v ilext ? ? vxtal ? 0.4v ((vdde5/2) ? 0.4v) v v 8 xtal current 7 i xtal 0.8 3 ma 9 total on-chip stray capacitance on xtal c s_xtal ?1.5pf 10 total on-chip stray capacitance on extal c s_extal ?1.5pf 11 crystal manufacturer?s recommended capacitive load c l see crystal specification see crystal specification pf 12 discrete load capacitance to be connected to extal c l_extal ?2*c l ? c s_extal ? c pcb_extal 8 pf 13 discrete load capacitance to be connected to xtal c l_xtal ?2*c l ? c s_xtal ? c pcb_xtal 8 pf 14 pll lock time 9 t lpll ?750 s 15 dual controller (1:1) clock skew (between clkout and extal) 10, 11 t skew ?2 2 ns 16 duty cycle of reference t dc 40 60 % 17 frequency un-lock range f ul ? 4.0 4.0 % f sys 18 frequency lock range f lck ? 2.0 2.0 % f sys 19 clkout period jitter, 12, 13 measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 5.0 .01 % f clkout
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 20 3.10 eqadc electrical characteristics 20 frequency modulation range limit 14 (f sys max must not be exceeded) c mod 0.8 2.4 %f sys 21 ico frequency. f ico =[f ref *(mfd+4)]/(prediv+1) 15 f ico 48 f sys mhz 22 predivider output frequency (to pll) f prediv 4f max mhz 1 all internal registers retain data at 0 hz. 2 up to the maximum frequency rating of the device (see ta bl e 1 ). 3 ?loss of reference frequency? is the reference frequency detected internally, which transitions the pll into self clocked mode. 4 self clocked mode (scm) frequency is th e frequency that the pll operates at when the reference frequency falls below f lor . this frequency is measured on the clkout pin with the divider set to divide-by-2 of the system clock. note: in scm, the mfd and prediv have no effect and the rfd is bypassed. 5 this parameter is meant for those who do not use quartz crystals or resonators, but can osc, in crystal mode. in that case, v extal ? v xtal >= 400mv criteria has to be met for oscillator?s comparator to produce output clock. 6 this parameter is meant for those who do not use quartz crystals or resonators, but can osc, in crystal mode. in that case, v xtal ?v extal >= 400mv criteria has to be met for oscillator?s comparator to produce output clock. 7 i xtal is the oscillator bias current out of the xtal pin with both extal and xtal pins grounded. 8 c pcb_extal and c pcb_xtal are the measured pcb stray capacitan ces on extal and xtal, respectively 9 this specification applies to the period r equired for the pll to relock after changi ng the mfd frequency control bits in the synthesizer control register (sy ncr). from power up with crystal oscillator reference, the lock time will also include the crys tal startup time. 10 pll is operating in 1:1 pll mode. 11 vdde = 3.0 to 3.6v 12 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddsyn and v sssyn and variation in crystal oscillator frequency increase the jitter percentage for a given interval. clkout divider set to divide-by-2. 13 values are with frequency modulation disabled. if frequency modulation is enabled, jitter is the sum of jitter + cmod. 14 modulation depth selected must not result in f sys value greater than the f sys maximum specified value. 15 f sys = f ico / (2 rfd ) table 13. eqadc conversion specifications (operating) num characteristic symbol min max unit 1 adc clock (adclk) frequency 1 f adclk 112mhz 2 conversion cycles differential single ended cc 13+2 (or 15) 14+2 (or 16) 13+128 (or 141) 14+128 (or 142) adclk cycles 3 stop mode recovery time 2 t sr 10 ? s 4 resolution 3 ?1.25 ? mv 5 inl: 6 mhz adc clock inl6 ?4 4 counts 3 6 inl: 12 mhz adc clock inl12 ?8 8 counts table 12. hip7 fmpll electrica l specifications (continued) (v ddsyn = 3.0v to 3.6 v, v ss = v sssyn = 0 v, t a = t l to t h ) num characteristic symbol min. value max. value unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 21 3.11 h7fa flash memory electrical characteristics 7 dnl: 6 mhz adc clock dnl6 ?3 4 3 4 counts 8 dnl: 12 mhz adc clock dnl12 ?6 4 6 4 counts 9 offset error with calibration offwc ?4 5 4 5 counts 10 full scale gain error with calibration gainwc ?8 6 8 6 counts 11 disruptive input injection current 7, 8, 9, 10 i inj ?1 1 ma 12 incremental error due to injection current. all channels have same 10k ? < rs <100k ? channel under test has rs=10k ? , i inj =i injmax ,i injmin e inj ?4 4 counts 13 total unadjusted error for single ended conversions with calibration 11, 12, 13, 14, 15 tue ?4 4 counts 1 conversion characteristics vary with f adclk rate. reduced conversion accuracy occurs at maximum f adclk rate. the maximum value is based on 800ks/s and the minimum value is based on 20mhz oscillator clock frequency divided by a maximum 16 factor. 2 stop mode recovery time is the time from the setting of either of the enable bits in the adc control register to the time that the adc is ready to perform conversions. 3 at vrh ? vrl = 5.12 v, one lsb = 1.25 mv = one count 4 guaranteed 10-bit monotonicity 5 the absolute value of the offset error without calibration 100 counts. 6 the absolute value of the full scale gain error without calibration 120 counts. 7 below disruptive current conditions, the channel being stressed has conversion values of 0x3ff for analog inputs greater than v rh and 0x000 for values less than v rl . this assumes that v rh v dda and v rl v ssa due to the presence of the sample amplifier. other channels are not af fected by non-disruptive conditions. 8 exceeding limit may cause conversion error on stressed channels a nd on unstressed channels. transitions within the limit do not affect device reliability or cause permanent damage. 9 input must be current limited to the val ue specified. to determine the value of th e required current-limiting resistor, calcula te resistance values using v posclamp = v dda + 0.5v and v negclamp = ? 0.3 v, then use the larger of the calculated values. 10 condition applies to two adjacent pads on the internal pad. 11 the tue specification will always be better than the sum of the inl, dnl, offset, and gain errors due to canceling errors. 12 tue does not apply to differential conversions. 13 measured at 6 mhz adc clock. tue with a 12 mhz adc clock is: ?16 counts < tue < 16 counts. 14 tue includes all internal device error such as internal reference variation (75% ref, 25% ref) 15 depending on the customer input impedance, the analog input leak age current (dc electrical specification 35a) may affect the actual tue measured on analog channels an12, an13, an14, an15. table 14. flash program and erase specifications 1 num characteristic symbol min typ initial max 2 max 3 unit 3 double word (64 bits) program time 4 t dwprogram ?10?500 s 4 page program time 4 t pprogram ?2244 5 500 s 7 16 kbyte block pre-program and erase time t 16kpperase ? 265 400 5000 ms 9 48 kbyte block pre-program and erase time t 48kpperase ? 340 400 5000 ms table 13. eqadc conversion specifications (operating) (continued) num characteristic symbol min max unit
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 22 table 16 shows the flash_biu settings versus frequency of operation. refer to the device reference manual for definitions of these bit-fields. 10 64 kbyte block pre-program and erase time t 64kpperase ? 400 500 5000 ms 8 128 kbyte block pre-program and erase time t 128kpperase ? 500 1250 15,000 ms 11 minimum operating frequency for program and erase operations 6 ?25???mhz 1 typical program and erase times assume nominal supply values and operation at 25 o c. 2 initial factory condition: 100 program/erase cycles, 25 o c, typical supply voltage, 80mhz minimum system frequency. 3 the maximum erase time occurs after the specified number of program/erase cycles. this maximum value is characterized but not guaranteed. 4 actual hardware programming times. this does not include software overhead. 5 page size is 256 bits (8 words). 6 read frequency of the flash can be up to the maximum operating frequency of the device. there is no minimum read frequency condition. table 15. flash eeprom module life (full temperature range) num characteristic symbol min typical 1 1 typical endurance is evaluated at 25c. product qualificati on is performed to the minimum specification. for additional information on the freescale definition of typical endurance, please refer to engineering bulletin eb619 ?typical endurance for nonvolatile memory.? unit 1a number of program/erase cycles per block for 16 kbyte, 48 kbyte, and 64 kbyte blocks over the operating temperature range (t j ) p/e 100,000 ? cycles 1b number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) p/e 10,000 100,000 cycles 2 data retention blocks with 0 ? 1,000 p/e cycles blocks with 1,001 ? 100,000 p/e cycles retention 20 5 ?years table 16. flash_biu settings vs. frequency of operation maximum frequency (mhz) apc rwsc wwsc dpfen ipfen pflim bfen up to and including 82 mhz 1 1 this setting allows for 80 mhz system clock with 2% frequency modulation. 0b001 0b001 0b01 0b00, 0b01, or 0b11 2 0b00, 0b01, or 0b11 2 0b000- 0b110 3 0b0, 0b1 4 up to and including 102 mhz 5 0b001 0b010 0b01 0b00, 0b01, or 0b11 2 0b00, 0b01, or 0b11 2 0b000- 0b110 3 0b0, 0b1 4 up to and including132 mhz 6 0b010 0b011 0b01 0b00, 0b01, or 0b11 2 0b00, 0b01, or 0b11 2 0b000- 0b110 3 0b0, 0b1 4 default setting after reset 0b111 0b111 0b11 0b00 0b00 0b000 0b0 table 14. flash program and erase specifications 1 (continued) num characteristic symbol min typ initial max 2 max 3 unit
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 23 3.12 ac specifications 3.12.1 pad ac specifications 2 for maximum flash performance, this should be set to 0b11. 3 for maximum flash performance, this should be set to 0b110. 4 for maximum flash performance, this should be set to 0b1. 5 this setting allows for 100 mhz system clock with 2% frequency modulation. 6 this setting allows for 128 mhz system clock with 2% frequency modulation. table 17. pad ac specifications (vddeh = 5.0v, vdde = 1.8v) 1 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at f sys = 132mhz, vdd = 1.35v to 1.65v, vdde = 1.62v to 1.98v, vddeh = 4.5v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th. num pad src/dsc out delay 2, 3, 4 (ns) 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 out delay is shown in figure 3 . add a maximum of one system clock to the output delay for delay with respect to system clock. 4 delay and rise/fall are measured to 20% or 80% of the respective signal. rise/fall 4 , 5 (ns) 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. load drive (pf) 1 slow high voltage (sh) 11 26 15 50 82 60 200 01 75 40 50 137 80 200 00 377 200 50 476 260 200 2 medium high voltage (mh) 11 16 8 50 43 30 200 01 34 15 50 61 35 200 00 192 100 50 239 125 200 3 fast 00 3.1 2.7 10 01 2.5 20 10 2.4 30 11 2.3 50 4 pull up/down (3.6v max) ? ? 7500 50 5 pull up/down (5.5v max) ? ? 9000 50
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 24 table 18. de-rated pad ac specifications (vddeh = 3.3v, vdde = 3.3v) 1 1 these are worst case values that are estimated from simulati on and not tested. the values in the table are simulated at f sys = 132mhz, vdd = 1.35v to 1.65v, vdde = 3.0v to 3.6v, vddeh = 3.0v to 3.6v , vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th. num pad src/dsc out delay 2, 3, 4 (ns) 2 this parameter is supplied for reference and is not guaranteed by design and not tested. 3 delay and rise/fall are measured to 20% or 80% of the respective signal. 4 out delay is shown in figure 3 . add a maximum of one system clock to the output delay for delay with respect to system clock. rise/fall 3 , 5 (ns) 5 this parameter is guaranteed by characterization before qualification rather than 100% tested. load drive (pf) 1 slow high voltage (sh) 11 39 23 50 120 87 200 01 101 52 50 188 111 200 00 507 248 50 597 312 200 2 medium high voltage (mh) 11 23 12 50 64 44 200 01 50 22 50 90 50 200 00 261 123 50 305 156 200 3fast 003.22.410 01 2.2 20 10 2.1 30 11 2.1 50 4 pull up/down (3.6v max) ? ? 7500 50 5 pull up/down (5.5v max) ? ? 9500 50
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 25 figure 3. pad output delay 3.13 ac timing 3.13.1 reset and configuration pin timing table 19. reset and configuration pin timing 1 1 reset timing specified at f sys = 132mhz, vddeh = 3.0v to 5.25v, vdd = 1.35v to 1.65v, t a = tl to th. num characteristic symbol min max unit 1 reset pulse width t rpw 10 ? t cyc 2 reset glitch detect pulse width t gpw 2?t cyc 3 pllcfg, bootcfg, wkpcfg, rstcfg setup time to rstout valid t rcsu 10 ? t cyc 4 pllcfg, bootcfg, wkpcfg, rstcfg hold time from rstout valid t rch 0?t cyc vdd/2 v oh v ol rising edge out delay falling edge out delay pad internal data input signal pad output
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 26 figure 4. reset and configuration pin timing 3.13.2 ieee 1149.1 interface timing table 20. jtag pin ac electrical characteristics 1 1 these specifications apply to jtag boundary scan only. jtag timi ng specified at vdd = 1.35v to 1.65v, vdde = 3.0v to 3.6v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 30pf with dsc = 0b10, src = 0b11. see ta bl e 2 1 for functional specifications. num characteristic symbol min max unit 1tck cycle time t jcyc 100 ? ns 2 tck clock pulse width (measured at vdde/2) t jdc 40 60 ns 3 tck rise and fall times (40% ? 70%) t tckrise ?3ns 4 tms, tdi data setup time t tmss, t tdis 5?ns 5 tms, tdi data hold time t tmsh, t tdih 25 ? ns 6 tck low to tdo data valid t tdov ?20ns 7 tck low to tdo data invalid t tdoi 0?ns 8 tck low to tdo high impedance t tdohz ?20ns 9 jcomp assertion time t jcmppw 100 ? ns 10 jcomp setup time to tck low t jcmps 40 ? ns 11 tck falling edge to output valid t bsdv ?50ns 12 tck falling edge to output valid out of high impedance t bsdvz ?50ns 13 tck falling edge to output high impedance t bsdhz ?50ns 14 boundary scan input valid to tck rising edge t bsdst 50 ? ns 15 tck rising edge to boundary scan input invalid t bsdht 50 ? ns 1 2 reset rstout wkpcfg pllcfg 3 4 bootcfg rstcfg
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 27 figure 5. jtag test clock input timing figure 6. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 28 figure 7. jtag jcomp timing tck jcomp 9 10
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 29 figure 8. jtag boundary scan timing tck output signals input signals output signals 11 12 13 14 15
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 30 3.13.3 nexus timing figure 9. nexus output timing table 21. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug func tionality. all nexus timing rela tive to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at vdd = 1.35v to 1.65v, vdde = 2.25v to 3.6v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 30pf with dsc = 0b10. num characteristic symbol min max unit 1 mcko cycle time t mcyc 1 2 2 the nexus aux port can only run up to 82mhz. the npc_pcr[mc ko_div] must be set to divide by 2 if the system frequency is above 82mhz 8t cyc 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo data valid 3 3 mdo, mseo , and evto data is held valid until next mcko low cycle. t mdov ?1.5 3.0 ns 4 mcko low to mseo data valid 3 t mseov ?1.5 3.0 ns 5 mcko low to evto data valid 3 t evtov ?1.5 3.0 ns 6 evti pulse width t evtipw 4.0 ? t tcyc 7 evto pulse width t evtopw 1t mcyc 8 tck cycle time t tcyc 4 4 4 the maximum frequency must be limited to approximately 16 mh z (vdde= 2.25 to 3.0 volts) or 22 mhz (vdde= 3.0 to 3.6 volts) to meet the ti ming specification for t jov of 0.2 x t jcyc as outlined in the ieee-ist o 5001-2003 specification. ?t cyc 9 tck duty cycle t tdc 40 60 % 10 tdi, tms data setup time t ntdis, t ntmss 8?ns 11 tdi, tms data hold time t ntdih, t ntmsh 5?ns 12 tck low to tdo data valid t jov vdde = 2.25 to 3.0 volts 0 12 ns vdde = 3.0 to 3.6 volts 0 9 ns 13 rdy valid to mcko 5 5 the rdy pin timing is asynchronous to mcko. the timing is guaranteed by design to function correctly. ???? 1 2 3 4 5 mcko mdo mseo evto output data valid
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 31 figure 10. nexus tdi, tms, tdo timing tdo 10 11 tms, tdi 12 tck
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 32 3.13.4 external bus interface (ebi) timing table 22. bus operation timing 1 # characteristic/de scription symbol 40 mhz (ext. bus) 2 56 mhz (ext. bus) 2 66 mhz (ext. bus) 2 unit notes min max min max min max 1clkout period t c 25.0 ? 17.9 ? 15.2 ? ns signals are measured at 50% vdde. 2 clkout duty cycle t cdc 45% 55% 45% 55% 45% 55% t c 3 clkout rise time t crt ?? 3 ?? 3 ?? 3 ns 4 clkout fall time t cft ?? 3 ?? 3 ?? 3 ns 5 clkout positive edge to output signal invalid or high z (hold time) addr[8:31] bdip bg 4 br 5 cs[0:3] data[0:31] oe rd_wr ta tea ts tsiz[0:1] we [0:3]/be [0:3] t coh 1.0 6 / 1.5 ?1.0 6 / 1.5 ?1.0 6 / 1.5 ?nshold time selectable via siu_eccr[ebts] bit: ebts=0/ebts=1 6 clkout posedge to output signal valid (output delay) addr[8:31] bdip bg 4 br 5 cs[0:3] data[0:31] oe rd_wr ta tea ts tsiz[0:1] we [0:3]/be [0:3] t cov ?10.0 6 / 11.0 ?7.5 6 / 8.5 ?6.0 6 / 7.0 ns output valid time selectable via siu_eccr[ebts] bit: ebts=0/ebts=1
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 33 figure 11. clkout timing 7 input signal valid to clkout posedge (setup time) addr[8:31] bb bg 5 br 5 data[0:31] rd_wr ta tea ts tsiz[0:1] t cis 10.0?7.0?5.0?ns 8 clkout posedge to input signal invalid (hold time) addr[8:31] bb bg 5 br 5 data[0:31] rd_wr ta tea ts tsiz[0:1] t cih 1.0 ? 1.0 ? 1.0 ? ns 1 ebi timing specified at vdd = 1.35v to 1.65v, vdde = 1.6v to 3.6v (unless stated otherwise), vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 30pf with dsc = 0b10. 2 the external bus is limited to half the speed of the internal bus. 3 refer to fast pad timing in ta b l e 1 7 and ta b l e 1 8 (different values for 1.8v vs 3.3v). 4 internal arbitration 5 external arbitration 6 the ebts=0 timings are only valid/ tested at vdde=2.25-3. 6v, whereas ebts=1 timings are valid/tested at 1.6?3.6v. table 22. bus operation timing 1 (continued) # characteristic/de scription symbol 40 mhz (ext. bus) 2 56 mhz (ext. bus) 2 66 mhz (ext. bus) 2 unit notes min max min max min max 1 2 2 3 4 clkout vdde/2 vol_f voh_f
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 34 figure 12. synchronous output timing 6 5 5 clkout bus 5 output signal output vdde/2 vdde/2 vdde/2 vdde/2 6 5 output signal vdde/2 6
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 35 figure 13. synchronous input timing 7 8 clkout input bus 7 8 input signal vdde/2 vdde/2 vdde/2
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 36 3.13.5 external interrupt timing (irq pin) figure 14. external interrupt timing figure 15. external interrupt setup timing table 23. external interrupt timing 1 1 irq timing specified at f sys = 132mhz, vdd = 1.35v to 1.65 v, vddeh = 3.0v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 200pf with src = 0b11. num characteristic symbol min max unit 1 irq pulse width low t ipwl 3?t cyc 2 irq pulse width high t ipwh 3?t cyc 3 irq edge to edge time 2 2 applies when irq pins are configured for rising edge or falling edge events, but not both. t icyc 6?t cyc irq 1 2 3 clkout irq 4
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 37 3.13.6 etpu timing figure 16. etpu timing figure 17. etpu input/output timing table 24. etpu timing 1 1 etpu timing specified at f sys = 132mhz, vdd = 1.35v to 1.65v, vddeh = 3.0v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 200pf with src = 0b11. num characteristic symbol min max unit 1 etpu input channel pulse width t icpw 4?t cyc 2 etpu output channel pulse width t ocpw 2?t cyc 1 2 etpu output etpu input and tcrclk clkout 3 4 etpu output etpu input and tcrclk
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 38 3.13.7 emios (mts) timing 3.13.8 dspi timing table 25. mts timing 1 1 mts timing specified at f sys = 132mhz, vdd = 1.35v to 1.65v, vddeh = 3.0v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 50pf with src = 0b11. num characteristic symbol min max unit 1 emios (mts) input pulse width t mipw 4?t cyc 2 emios (mts) output pulse width t mopw 1?t cyc table 26. dspi timing 1 num characteristic symbol 80 mhz 112 mhz 132 mhz unit min max min max min max 1 sck cycle time 2,3 t sck 25ns 2.9ms 17.9ns 2.0ms 15.2ns 1.7ms ? 2 pcs to sck delay 4 t csc 23 ? 15 ? 13 ? ns 3 after sck delay 5 t asc 22 ? 14 ? 12 ? ns 4 sck duty cycle t sdc t sck /2 ?2ns t sck /2 + 2ns ?? ? ? ns 5 slave access time (ss active to sout driven) t a ? 25 ? 25 ? 25 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ? 25 ? 25 ns 7 pcsx to pcss time t pcsc 4?4? 4 ?ns 8pcss to pcsx time t pasc 5?5? 5 ?ns 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) t sui 20 2 ?4 20 ? ? ? ? 20 2 3 20 ? ? ? ? 20 2 6 20 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 6 master (mtfe = 1, cpha = 1) t hi ?4 7 21 ?4 ? ? ? ? ?4 7 14 ?4 ? ? ? ? ?4 7 12 ?4 ? ? ? ? ns ns ns ns
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 39 figure 18. dspi classic spi timing ? master, cpha = 0 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha=0) master (mtfe = 1, cpha=1) t suo ? ? ? ? 5 25 18 5 ? ? ? ? 5 25 14 5 ? ? ? ? 5 25 13 5 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho ?5 5.5 8 ?5 ? ? ? ? ?5 5.5 4 ?5 ? ? ? ? ?5 5.5 3 ?5 ? ? ? ? ns ns ns ns 1 dspi timing specified at vdd = 1.35v to 1.65v, vddeh = 3.0v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 50pf with src = 0b11. 2 the minimum sck cycle time restricts the baud rate selection for given system cl ock rate. these numbers are calculated based on two mpc55xx devices communicating over a dspi link. 3 the actual minimum sck cycle time is limited by pad performance. 4 the maximum value is programmable in dspi_ctarx[pssck] and dspi_ctarx[cssck] 5 the maximum value is programmable in dspi_ctarx[pasc] and dspi_ctarx[asc] 6 this number is calculated assuming the smpl_pt bit field in dspi_mcr is set to 0b10. table 26. dspi timing 1 (continued) num characteristic symbol 80 mhz 112 mhz 132 mhz unit min max min max min max data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 40 figure 19. dspi classic spi timing ? master, cpha = 1 figure 20. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1)
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 41 figure 21. dspi classic spi timing ? slave, cpha = 1 figure 22. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1)
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 42 figure 23. dspi modified transfer format timing ? master, cpha = 1 figure 24. dspi modified transfer format timing ? slave, cpha =0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 43 figure 25. dspi modified transfer format timing ? slave, cpha =1 figure 26. dspi pcs strobe (pcss ) timing 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) pcsx 7 8 pcss
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 44 3.13.9 eqadc ssi timing figure 27. eqadc ssi timing table 27. eqadc ssi timing characteristics (pads at 3.3v or at 5.0v) 1 1 ss timing specified at f sys = 132mhz, vdd = 1.35v to 1.65v, vddeh = 3.0v to 5.5v, vdd33 and vddsyn = 3.0v to 3.6v, t a = tl to th, and cl = 50pf with src = 0b11. cload = 25pf on all outputs. pad drive strength set to maximum. num rating symbol min typ max unit 1 fck frequency 2, 3 2 maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays. 3 fck duty is not 50% when it is generated through the division of the system clock by an odd number. f fck 1/17 ? 1 / 2f sys_clk 2fck period (t fck = 1/ f fck ) t fck 2? 17t sys_clk 3 clock (fck) high time t fckht t sys_clk ? 6.5 ? 9* t sys_clk + 6.5 ns 4 clock (fck) low time t fcklt t sys_clk ? 6.5 ? 8* t sys_clk + 6.5 ns 5 sds lead/lag time t sds_ll ?7.5 ? +7.5 ns 6 sdo lead/lag time t sdo_ll ?7.5 ? +7.5 ns 7 eqadc data setup time (inputs) t eq _ su 22 ? ? ns 8 eqadc data hold time (inputs) t eq_ho 1? ? ns 1st (msb) 2nd 25th 26th 1st (msb) 2nd 25th 26th 8 7 5 6 4 5 4 2 3 fck sds sdo external device data sample at sdi eqadc data sample at fck falling edge fck rising edge
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 45 3.14 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at 3.3 v. note that the timing specifications for the mii signals are independent of system clock frequency (part speed designation). 3.14.1 mii receive signal timing (rxd [3:0], rx_dv, rx_er, and rx_clk) the receiver functions co rrectly up to a rx_clk maximum fre quency of 25 mhz +1%. there is no minimum frequency requirement. in addition, th e processor clock frequency must exceed 4 the rx_clk frequency. table 28 lists mii receive channel timings. figure 28 shows mii receive sign al timings listed in table 28 . figure 28. mii receive signal timing diagram table 28. mii receive signal timing num characteristic min max unit 1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5 ? ns 2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5 ? ns 3 rx_clk pulse width high 35% 65% rx_clk period 4 rx_clk pulse width low 35% 65% rx_clk period m1 m2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er m3 m4
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 46 3.14.2 mii transmit signal timing (t xd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_c lk maximum frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the pr ocessor clock frequency must exceed twice the tx_clk frequency. the transmit outputs (txd[3:0], tx_en, tx_er) can be programmed to transiti on from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter of the device reference manual for details of this option and how to enable it. table 29 lists mii transmit channel timings. figure 29 shows mii transmit si gnal timings listed in table 29 . figure 29. mii transmit signal timing diagram table 29. mii transmit signal timing num characteristic min max unit 5 tx_clk to txd[3:0], tx_en, tx_er invalid 5 ? ns 6 tx_clk to txd[3:0], tx_en, tx_er valid ? 25 ns 7 tx_clk pulse width high 35% 65% tx_clk period 8 tx_clk pulse width low 35% 65% tx_clk period m6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er m5 m7 m8
electrical characteristics mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 47 3.14.3 mii async inputs sign al timing (crs and col) table 30 lists mii asynchronous inputs signal timing. figure 30 shows mii asynchronous i nput timings listed in table 30 . figure 30. mii async inputs timing diagram 3.14.4 mii serial management ch annel timing (mdio and mdc) table 31 lists mii serial management channel timings. the fec functio ns correctly with a maximum mdc frequency of 2.5 mhz. figure 31 shows mii serial management channel timings listed in table 31 . table 30. mii async inputs signal timing num characteristic min max unit 9 crs, col minimum pulse width 1.5 ? tx_clk period table 31. mii serial management channel timing num characteristic min max unit 10 mdc falling edge to mdio output invalid (minimum propagation delay) 0 ? ns 11 mdc falling edge to mdio output valid (max prop delay) ? 25 ns 12 mdio (input) to mdc rising edge setup 10 ? ns 13 mdio (input) to mdc rising edge hold 0 ? ns 14 mdc pulse width high 40% 60% mdc period 15 mdc pulse width low 40% 60% mdc period crs, col m9
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice electrical characteristics freescale semiconductor 48 figure 31. mii serial management channel timing diagram figure 32. reset and c onfiguration pin timing mdc (output) mdio (output) m12 m13 mdio (input) m10 m14 m15 m11 clkout 5 6 reset rstout 6 5
mechanicals mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 49 4 mechanicals 4.1 pinouts 4.1.1 mpc5553 416 pbga pinout figure 33 , figure 34 , and figure 35 show the pinout for the mpc 5553 416 pbga package. while the mpc5553 and the mpc5554/mpc5565/mpc5 566 are pin-compatible, the mpc5553 ball map is shown here to highlight the balls that are not connected to any signal on the mcp5553 (the etpub[0:31] and tsiz[0:1]). the alternate ethernet signals that are multiplexed with the data bus are not shown for the mpc5553. note some pins have names that include f unctions that are not available on all family members. for example, ball r25 of the 416 bga package is named ?sina,? but the mpc5553 does not have a dspi_a module. in this case, the sina pin can only be used for its alternate functi ons of gpio94 or pcsc2. see the specific device reference ma nual for functions available on each device in the family.
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice mechanicals freescale semiconductor 50 figure 33. mpc5553 416 package no connect. ac22 & ad23 reserved nc_37 vss 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 vssa0 an15 mdo11 mdo8 vdd vdd33 vss a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 an12 mdo5 mdo2 vss vdde7 tck tdi d vdd vdde7 tms tdo test e mseo0 jcomp evti evto f mseo1 mcko g rdy h j vss vss vss vss vdde7 vdde7 vdde7 vdde7 k vss vss vss vss vss vss vss vdde7 l vss vdde2 vdde2 vss vss vss vss vdde7 sinb m bdip vss tea vdde2 vdde2 vss vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss vss vss vss vss pcsa3 pcsb4 sckb pcsb2 p we3 vss we2 we1 we0 vdde2 vdde2 vss vss vss vss vss pcsb5 souta sina scka r vdde2 vdde2 nc_34 rd_wr vdde2 vdde2 vss vdde2 vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp t vdde2 nc_35 ta vdd33 vss vdde2 vdde2 vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash u ts cntxc rxda rstout v rxdb cnrxc txdb reset w vdde2 y extal aa vdde2 vdd xtal ab vdde2 vss vdd vdde2 vdde5 nc_36 vss vdd vrc33 ac vss vdd vdd33 cntxa vdde5 nc_37 vss vdd vdd33 ad br vss vdd oe bg cnrxa vdde5 clkout vss vdd ae vss vdd vdde2 vdde2 nc_38 cntxb cnrxb vdde5 vss af a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 an10 an21 an0 an1 etrig 1 gpio 205 etrig 0 etpua 30 etpua 31 vddeh 9 vddeh 8 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a vddeh 6 gpio 204 gpio 203 addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk version 2.1 ? 13 july 2004 note: no connects (x = 1 to 38) nc_x ref bypc nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 nc_10 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_23 nc_27 nc_31 nc_18 nc_19 nc_17 nc_20 nc_21 nc_22 nc_24 nc_25 nc_26 nc_28 nc_29 nc_30 nc_32 nc_33 nc_36
mechanicals mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 51 figure 34. mpc5553 416 package, left side vss 12345678910111213 an35 vstby an37 an11 vdda1 an16 an5 vrh an23 an27 an28 a vdd an32 vss an36 an39 an19 an20 an4 an22 an26 an31 b vdd33 an33 vdd vss an8 an17 vssa1 an3 an7 vrl an25 an30 c an34 vdd vss an38 an9 an18 an2 an6 an24 an29 d vdd e f g h j vss vss vss vss k vss vss vss vss l vss vdde2 vdde2 vss m bdip vss tea vdde2 vdde2 vss n cs3 vss cs2 cs1 cs0 vdde2 vdde2 vss p we3 vss we2 we1 we0 vdde2 vdde2 vss r vdde2 vdde2 nc_34 rd_wr vdde2 vdde2 vss vdde2 t vdde2 nc_35 ta vdd33 vss vdde2 vdde2 u ts v w vdde2 y aa vdde2 ab vdde2 vss vdd vdde2 vss vdd vdd33 br vss vdd oe ae vss vdd vdde2 vdde2 af 12345678910111213 an10 an21 an0 an1 etpua 30 etpua 31 vddeh 1 etpua 28 etpua 29 vddeh 1 etpua 24 etpua 27 etpua 26 etpua 23 etpua 22 etpua 25 etpua 21 etpua 20 etpua 19 etpua 18 etpua 17 etpua 16 etpua 15 etpua 14 etpua 13 etpua 12 etpua 11 etpua 10 etpua 9 etpua 8 etpua 7 etpua 6 etpua 5 etpua 4 etpua 3 etpua 2 etpua 1 etpua 0 tcrclk a addr 16 addr 18 addr 17 addr 8 addr 20 addr 19 addr 10 addr 9 addr 22 addr 21 addr 11 addr 24 addr 23 addr 12 addr 13 addr 25 addr 14 addr 15 addr 26 addr 27 addr 31 addr 28 addr 30 addr 29 data 16 data 18 data 17 data 19 data 24 data 21 data 25 data 26 data 20 data 23 data 27 data 28 data 22 gpio 207 gpio 206 data 0 data 29 data 30 data 31 data 8 data 9 data 2 data 4 data 6 data 1 data 3 data 11 data 10 data 13 data 5 data 7 ref bypc ad ac no connect. ac22 & ad23 reserved nc_37 version 2.1 ? 13 july 2004 note: no connects (x = 1 to 38) nc_x nc_36
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice mechanicals freescale semiconductor 52 figure 35. mpc5553 416 package, right side 14 15 16 17 18 19 20 21 22 23 24 25 26 vssa0 an15 mdo11 mdo8 vdd vdd33 vss vssa0 an14 mdo10 mdo7 mdo4 mdo0 vss vdde7 vdda0 an13 mdo9 mdo6 mdo3 mdo1 vss vdde7 vdd an12 mdo5 mdo2 vss vdde7 tck tdi vdde7 tms tdo test mseo0 jcomp evti evto mseo1 mcko rdy vdde7 vdde7 vdde7 vdde7 vss vss vss vdde7 vss vss vss vdde7 sinb vss vss vss vdde7 soutb pcsb3 pcsb0 pcsb1 vss vss vss vss pcsa3 pcsb4 sckb pcsb2 vss vss vss vss pcsb5 souta sina scka vdde2 vdde2 vss vss pcsa1 pcsa0 pcsa2 vpp vdde2 vdde2 vss vss pcsa4 txda pcsa5 vflash cntxc rxda rstout rxdb cnrxc txdb reset extal vdd xtal vdde5 nc_36 vss vdd vrc33 cntxa vdde5 nc_37 vss vdd vdd33 bg cnrxa vdde5 clkout vss vdd nc_38 cntxb cnrxb vdde5 vss a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 14 15 16 17 18 19 20 21 22 23 24 25 26 etrig 1 gpio 205 etrig 0 vddeh 9 vddeh 8 vddeh 6 gpio 204 gpio 203 data 15 data 12 data 14 emios 3 emios 1 emios 0 emios 6 emios 5 emios 4 emios 2 emios 10 emios 9 emios 7 emios 8 emios 15 emios 13 emios 11 emios 12 emios 17 emios 16 emios 14 emios 21 emios 22 emios 19 emios 18 emios 23 emios 20 vddeh 4 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk nc_1 nc_2 nc_3 nc_4 nc_5 nc_6 nc_7 nc_8 nc_9 nc_10 nc_11 nc_12 nc_13 nc_14 nc_15 nc_16 nc_23 nc_27 nc_31 nc_18 nc_19 nc_17 nc_20 nc_21 nc_22 nc_24 nc_25 nc_26 nc_28 nc_29 nc_30 nc_32 nc_33
mechanicals mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 53 4.1.2 mpc5553 324 pbga pinout figure 36 is a pinout for the mpc5553 324 pbga package. figure 36. mpc5553 324 package vss 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an28 vdd vstby an37 an11 vdda1 an1 an5 vrh vrl an27 an35 vssa0 mdo10 mdo8 vdd vdd33 vss a vdd33 an31 vss vdd an36 an39 an19 an0 an23 an26 an32 vssa0 mdo9 mdo7 mdo4 mdo0 vss vdde7 b an30 vss vdd an8 an17 an21 an3 an7 an22 an25 an33 vdda0 an14 mdo5 mdo2 mdo1 vss vdde7 vdd c an29 vss vdd an38 an10 an18 an2 an6 an24 an15 mdo6 vss vdde7 tck tdi d vdde7 tms tdo test e vdde7 jcomp evti evto f rdy g vss vss vss vss vss vdde7 vss vss vss vss vss vss vss vss vss vss vss vss sinb h vss vdde2 vdde2 vss vss vss soutb pcsb3 pcsb0 pcsb1 j vss vss vss vdde2 vss vss pcsa3 pcsb4 sckb pcsb2 k vss vss vss vdde2 vss vss pcsb5 souta sina scka l bdip cs1 cs0 pcsa1 pcsa0 pcsa2 vpp m cs2 we1 we0 pcsa4 txda pcsa5 vflash n rd_wr cntxc rxda rstout p rxdb cnrxc txdb reset r ts t extal u vdde2 vdd xtal v vss vdd vdde2 vdde5 nc vss vdd vrc33 w vss vdd cntxa vdde5 nc vss vdd vdd33 y vss vdd cnrxa vdde5 clkout vss vdd aa vss vdd vdde2 vdde2 cntxb cnrxb vdde5 vss ab a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10111213141516171819202122 an9 an20 an16 vssa1 etpua 28 etpua 29 etpua 25 etpua 24 etpua 27 etpua 23 etpua 22 etpua 17 etpua 20 etpua 19 etpua 14 etpua 13 etpua 16 etpua 15 etpua 10 vddeh 1 etpua 6 gpio 204 gpio 203 vddeh 10 addr 16 addr 17 addr 18 addr 19 addr 20 addr 21 addr 12 addr 22 addr 23 addr 13 addr 25 addr 31 addr 15 addr 26 addr 24 addr 30 addr 28 addr 27 addr 29 data 0 data 1 data 8 data 3 data 9 data 4 data 13 gpio 206 data 5 data 10 data 11 data 12 data 14 data 15 data 7 emios 6 emios 2 emios 10 emios 15 vddeh 4 emios 12 emios 17 emios 16 emios 14 emios 22 emios 19 emios 18 emios 23 emios 20 emios 21 boot cfg1 vddeh 6 pll cfg1 boot cfg0 wkp cfg vrc vss vss syn vrc ctl pll cfg0 vdd syn rst cfg eng clk version 2.2p ? 13 july 2004 note: no connect. reserved (w18 & y19 are shorted to each other) nc w y aa ab mdo11 an12 an4 ref bypc an13 etpua 30 etpua 31 etpua 26 etpua 21 etpua 18 an34 vddeh 9 mdo3 etpua 11 etpua 12 etpua 2 etpua 7 etpua 8 etpua 0 tcrclk a etpua 3 etpua 4 etpua 9 etpua 5 etpua 1 mcko mseo0 mseo1 cs3 vdd33 ta vdde2 addr 14 vdde2 vdd33 emios 8 vdde2 vdde2 vdde2 gpio 207 data 2 data 6 emios 13 emios 9 emios 5 emios 3 oe emios 11 emios 7 emios 4 emios 1 emios 0
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice mechanicals freescale semiconductor 54 4.1.3 mpc5553 208 map bga pinout figure 37 is a pinout for the mpc5553 208 map bga package. note vddeh10 and vddeh6 are connected in ternally on the 208-ball package and are listed as vddeh6. figure 37. mpc5553 208 package vss 12345678910111213141516 an9 an11 vdda1 vrh vrl an12 mdo2 mdo0 vdd33 vss a vdd vss an38 an21 an0 an4 an22 an25 vdda0 an13 mdo3 mdo1 vss vdd b vss an17 an34 an16 an7 an23 an32 an33 an14 an15 vss mseo0 tck c vss an18 an2 an24 an31 an35 vss tms evto test d vdde7 tdi evti mseo1 e tdo mcko jcomp f soutb g vss vss vss vss vss vss vss vss vss vss vss vss pcsb1 h vss vss vss vss pcsb5 txda pcsa2 sckb j cntxc rxda rstout vpp k txdb cnrxc reset l rxdb m vss vdd vdd33 vss n vss vdd cntxa vdd vss vrc33 xtal p vss vdd cnrxa cnrxb vdd vss r vss vdd cntxb vdde5 vss t a b c d e f g h j k l m 12345678910111213141516 an6 an3 vssa1 etpua 30 etpua 31 etpua 28 etpua 29 etpua 26 etpua 24 etpua 27 etpua 25 etpua 21 etpua 23 etpua 22 etpua 17 etpua 14 vddeh 4 emios 16 emios 14 emios 15 emios 17 emios 19 emios 18 emios 23 emios 20 emios 12 pll cfg0 boot cfg1 eng clk 8 june 2005p note: no connect. r1 reserved for cs0 cs0 n p r t vssa0 an27 an28 etpua 19 etpua 20 etpua 7 etpua 15 etpua 16 etpua 6 etpua 11 etpua 12 etpua 13 tcrclk a pcsb3 sinb pcsb0 vdd33 oe vdd vdd vdd an5 an1 vstby vdd33 an30 vddeh 9 vddeh 6 pcsb2 pcsb4 pcsa3 etpua 18 an39 ref bypc an37 an36 vddeh 1 cs0 etpua 10 etpua 8 etpua 3 etpua 9 etpua 4 etpua 2 etpua 1 etpua 0 etpua 5 wkp cfg vss syn extal emios 21 emios 22 emios 10 emios 2 emios 8 emios 11 emios 13 emios 6 emios 9 emios 7 emios 3 emios 5 emios 4 emios 1 emios 0 pll cfg1 vrc ctl gpio 207 gpio 206 vdde2 vdd syn vdd
mechanicals mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 55 4.2 package dimensions 4.2.1 mpc5553 416-pin package figure 38 is a package drawing of th e mpc5553 416 pin tepbga package. figure 38. mpc5553 416 tepbga package
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice mechanicals freescale semiconductor 56 4.2.2 mpc5553 324-pin package figure 39 is a package drawing of th e mpc5553 324-pin tepbga package. figure 39. mpc5553 324 tepbga package
mechanicals mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 57 4.2.3 mpc5553 208-pin package figure 40 is a package drawing of th e mpc5553 208-pin map bga package. figure 40. mpc5553 208 map bga package
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice revision history freescale semiconductor 58 5 revision history table 32 provides a revision history of this document. table 32. revision history revision location(s) substantive change(s) rev. 0 this is the first released version of this document.
mpc5553 microcontroller data sheet, rev. 0 preliminary?subject to change without notice freescale semiconductor 59 this page is intentionally blank
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